1. Technical Field
The present invention is directed to the field of phase locked loops. More specifically, the invention provides an improved phase locked loop (xe2x80x9cPLLxe2x80x9d) having a controlled slew reference switch for controlling the phase deviation in the PLL output signal when the PLL switches from a primary input reference signal to a backup input reference signal.
2. Description of the Related Art
Phase locked loops are well-known elements in analog and digital circuit design. A phase locked loop operates by receiving an input reference clock signal and generating a localized oscillator signal that is synchronized with the reference clock signal. The local oscillator signal that is output from the PLL may operate at the same frequency as the reference clock signal or at some integer multiple of that frequency. A general description of the theory and operational characteristics of a PLL is contained in Couch, Digital and Analog Communication Systems, Fourth Edition, pp. 289-296.
FIG. 1 is a circuit diagram of a known PLL circuit 10A. This circuit 10A includes four primary elementsxe2x80x94a phase detector 14, an integrator 16, a voltage controlled oscillator (VCXO) 18, and a counter 26. This circuit 10A generates a local oscillator signal (PLL clock) 34 that is synchronized with an input reference clock signal 12, but which operates at a higher frequency than the reference clock 12. This is accomplished by feeding back a divided down version 38 of the local oscillator signal 34 to the phase detector 14, which then compares the phases of the reference clock signal 12 with the feedback signal 38.
The phase detector 14 compares the phases of the signals at its two inputs, and generates output pulse signals having pulse widths that correspond to the phase difference between the two input signals. These output pulse signals are then coupled to the integrator 16. The integrator 16 receives the pulses from the phase detector outputs and generates a voltage level at its output that is proportional to the pulse width of the phase pulses. This phase voltage is then provided as an input to the voltage controlled oscillator (VCXO) 32.
The voltage controlled oscillator 32 generates an output clock signal, PLL clock 34, which is characterized by a frequency that is proportional to the phase voltage from the integrator 16. This clock signal, PLL clock 34, is the localized oscillator signal that is synchronized with the reference clock 12. The PLL clock signal 34 is then fed back to one of the inputs of the phase detector 14 either directly, or via a counter 26.
The counter 26 is configured as a divide-by-N counter and it generates the PLL feedback signal 38, which is a frequency divided version of the PLL clock signal 34. By selecting an appropriate value of N, a circuit designer can select the frequency of the PLL clock signal 34 with respect to the external reference clock 12. For example, if the circuit designer desires to generate a synchronized version of the reference clock signal 12, but at a frequency 10 times greater than the reference clock signal 12, then the value of N would be 10.
In distributed communication systems, such as SONET/SDH networks that include a plurality of network elements coupled via fiber optic connections, there is often a need to distribute more than one reference clock to the various network elements in order to ensure synchronization of these elements. Typically, a system may include a primary input reference clock (which is used in normal operation) and a backup input reference clock (which is used when the primary clock fails.) These reference clocks typically exhibit independent phase characteristics due to the wander generated by each individual clock.
A PLL circuit is typically used to carry out this synchronization step. The PLL preferably locks onto the primary input reference clock. If the primary reference clock fails, however, then the PLL must lock onto the backup reference signal. But because of the independent phase characteristics of the two reference signals, this switch-over often results in a sudden reaction in the phase of the PLL output signal.
The problem with this sudden reaction by the PLL is that in certain telecommunication systems, such as the SONET/SDH systems noted above, there is a requirement that limits the reaction speed of such a PLL circuit under these conditions. One reason for this reaction speed requirement is that in such systems one PLL circuit may be feeding other PLL circuits in other parts of the system, which may in turn be feeding still other PLL circuits. If one of the PLLs in this chain of PLLs reacts too quickly, then the phase variation in its output signal may cause other PLLs (or clock recovery mechanisms) in the chain to become unlocked to their respective reference signals.
A typical solution to this problem is to slow down the loop bandwidth of the PLL so that in reaction to the switch-over from the primary to the backup reference clock, the loop does not violate the reaction speed requirement. This solution, however, degrades the locking ability of the PLL under certain conditions, such as under temperature variations, and therefore is not desirable.
A controlled slew reference switch circuit is provided for limiting the phase deviation of a phase locked loop (PLL) output signal in response to the PLL switching between a plurality of input reference clock signals. The PLL includes a phase detector for measuring the phase deviation between two input signals. The controlled slew reference switch circuit includes a transfer function generator that controls one or more selector circuits for operating the PLL in a normal mode of operation and a holdover mode of operation. In the normal mode of operation the PLL is locked to one of the reference clock signals, and the phase detector inputs are coupled to the reference clock signal and a PLL feedback signal. In the holdover mode of operation both inputs of the phase detector are coupled to the PLL feedback signal, thereby holding the PLL in its last operational state. By controlling the amount of time that the PLL operates in the holdover mode versus the normal mode of operation, the controlled slew reference switch circuit controls the gain of the PLL and thereby limits the phase deviation of the PLL output signal.
According to one aspect of the invention, a circuit is provided for controlling the phase deviation in a PLL output signal when a reference signal input to the PLL is switched between a first reference signal and a second reference signal. The circuit preferably includes: (1) a first selector for routing either the reference signal or a feedback signal to the PLL in response to a control signal; and (2) a transfer function generator for generating the control signal, wherein the control signal causes the first selector to switch between the reference clock signal and the feedback signal according to a predetermined transfer function in order to modulate the gain of the PLL and thereby control the phase deviation of the PLL output signal.
According to another aspect of the invention, a phased lock loop (PLL) circuit for locking onto either a primary input reference clock signal or a backup input reference clock signal is provided. The PLL includes: (1) a first switch for selecting a reference signal from one of the primary input reference clock signal or the backup input reference clock signal; (2) a phase detector having a pair of inputs for discriminating the phase difference between the two signals at the pair of inputs and for generating a corresponding phase pulse output; (3) an integrator coupled to the phase pulse output for generating a phase voltage; (4) a voltage controlled oscillator coupled to the phase voltage for generating a local oscillator signal that is synchronized to the reference clock signal; (5) a feedback circuit including a counter coupled to the local oscillator signal for generating a feedback signal; and (6) a controlled slew reference switch coupled between the first switch and the phase detector for controlling the gain of the PLL by switching the PLL between a normal mode of operation in which the reference signal and the feedback signal are coupled to the inputs of the phase detector and a holdover mode of operation in which the feedback signal is coupled to both inputs of the phase detector.
Still another aspect of the invention provides a phase locked loop for generating a synchronized output signal in response to a reference clock signal and a feedback signal, wherein the phase locked loop includes a controlled slew reference switch for selecting the reference clock signal from a plurality of external reference clocks and for controlling the phase deviation in the synchronized output signal by switching the phase locked loop between a normal mode of operation in which the phase locked loop is locked onto the reference clock signal and a holdover mode of operation in which the phase locked loop is held in a prior operational state.
Another aspect of the invention provides a phase locked loop (PLL), comprising: (1) a switch for selecting a primary reference clock signal or a backup reference clock signal and for outputting a selected reference clock; (2) a synchronization loop comprising a phase detector, a voltage controlled oscillator coupled to the phase detector for generating an output clock signal, and a feedback counter coupled between the voltage controlled oscillator and the phase detector for generating a feedback signal from the output clock signal; and (3) a PLL gain controller coupled to the switch and the synchronization loop for signaling the switch to select the primary reference clock signal or the backup reference clock signal and for switching the synchronization loop between a normal mode of operation in which the synchronization loop is locked onto the selected reference clock and a holdover mode of operation in which the synchronization loop is held in a prior operational state in order to control the gain of the synchronization loop.
Still another aspect of the invention relates to an improved phase locked loop of the type having a phase detector coupled to a reference clock signal and a feedback signal, a voltage controlled oscillator coupled to the phase detector for generating a synchronized output signal, and a feedback counter coupled to the synchronized output signal for generating the feedback signal. The improvement provides a controlled slew reference switch for switching the phase locked loop between a normal mode of operation in which the loop is locked to the reference clock signal and a holdover mode of operation in which the loop is held in a prior operational state, wherein the controlled slew reference switch switches the PLL between the normal mode of operation and the holdover mode of operation according to a transfer function in order to control the phase deviation of the synchronized output signal
It should be noted that these are just some of the many aspects of the present invention. Other aspects not specified will become apparent upon reading the detailed description of the drawings set forth below.